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ASAHI KASEI [AK2303LV] AK2303LV Dual PCM CODEC for PBX Analog Line Card GENERAL DESCRIPTION AK2303LV is a 3.3V dual PCM CODEC-Filter most suitable for analog line card of PBX switch. CODEC-Filter is compliant with G711/G712 recommendations. It includes Selectable A-law/u-law function, Internal Gain Adjustment from +6dB to -18dB by 1dB step control. All of these functions are controlled by the internal register accessed through the serial interface. Additionally, channel mute and A-law/u-law selection is controlled by the hard pin. PCM interface of AK2303LV supports Long Frame, Short Frame clock formats and GCI format. 4.096MHz, 2.048MHz bit clock input is available for PCM interface. - Dual FEATURE PCM CODEC and Filtering systems for PBX switch - Independent functions on each channel Controlled by the internal register or hard pin - Power Down Mode (Register setting) - Mute (Hard pin, register setting) - Gain Adjustment: +6 to -18dB (1dB step by register setting) - Selectable PCM Data Interface Timing: Long Frame / Short Frame/GCI - Selectable PCM Data Rate: 4.096MHz, 2.048MHz (Register setting) - OP Amp for External Gain Adjustment - A-law/u-law Select (Hard pin, Register setting) - Serial Interface for the internal register access - Power on Reset - Single Power Supply Voltage - +3.3V 0.3V - Low Power Consumption - 35mW typ PACKAGE - 28pinVSOP 9.8 x 7.6 mm (0.65mm pin pitch) MS0117-E-00 1 2001/09 ASAHI KASEI [AK2303LV] CONTENTS ITEMS - BLOCK DIAGRAM............................................. - PIN ASSIGNMENT............................................. - PIN CONDITION................................................ - PIN FUNCTION................................................. - FUNCTIONAL DESCRIPTION.............................. LONGFRAME/SHORTFRAME................ GCI.................................................... - MUTE.................................................... - RESET................................................... - SERIAL INTERFACE................................ - MODE SETTING....................................... - REGISTER....................................................... - RECOMMENDED OPERATING CONDITIONS........ PAGE 3 4 5 6 9 9 12 14 16 19 23 24 28 - CIRCUIT DESCRIPTION...................................... 8 - PCM INTERFACE...................................... 9 - GAIN ADJUSTMENT................................. 15 - POWER DOWN........................................ 17 - ABSOLUTE MAXIMUM RATINGS......................... 28 - ELECTRICAL CHARACTERISTICS....................... 28 - APPLICATION CIRCUIT EXAMPLE....................... 37 - PACKAGE INFORMATION.................................. 39 2303-E-00 2 2001/09 ASAHI KASEI [AK2303LV] BLOCK DIAGRAM GST0 VFTN0 AMPT0 GA0T AAF0 CODEC CH0 PCMI/F FS0 VR0 VFR0 GSR0 GST1 VFTN1 GA0R SMF0 DX DR FS AMPR0 BCLK GA1T AMPT1 AAF1 CODEC CH1 FS1 VR1 VFR1 GSR1 GA1R AMPR1 SMF1 VREF LPC BGREF PLL VDD VSS Power on Reset MODE TEST ALAWN MUTE1 MUTE0 Serial I/F SCLK DATA CSN RXVlm0 Internal Register TXVlm1 TXVlm0 RXVlm1 PWDN A/u_SEL R i 2303-E-00 3 2001/09 ASAHI KASEI [AK2303LV] PIN ASSIGNMENT TEST VFTN1 GST1 GSR1 VFR1 VR1 ALAWN AVDD DVDD FS BCLK DX DR MUTE1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VREF MODE VFTN0 GST0 GSR0 VFR0 AVSS DVSS VR0 LPC CSN DATA SCLK MUTE0 2303-E-00 4 2001/09 ASAHI KASEI [AK2303LV] PIN CONDITION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Name TEST VFTN1 GST1 GSR1 VFR1 VR1 ALAWN AVDD DVDD FS BCLK DX DR MUTE1 MUTE0 SCLK DATA CSN LPC VR0 DVSS AVSS VFR0 GSR0 GST0 VFTN0 MODE I/O I I O O I O I I I O I I I I I/O I O O I O O I I Pin type (*2) Analog Analog Analog Analog Analog CMOS AC load (MAX.) DC load (MIN.) Outout status (Power down mode) Remarks Tied to AVSS 50pF 50pF 50pF 10k(*1) 10k(*1) 10k Hi-Z Hi-Z Hi-Z CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Analog Analog 15pF Hi-Z 15pF Hi-Z (Input) 0.22uF 50pF 10k Hi-Z Analog Analog Analog Analog (*2) 50pF 50pF 10k(*1) 10k(*1) Hi-Z Hi-Z 28 VREF O Analog *1) DC load(MIN.) includes a feedback resistance of input/output op-amp. *2) Please tie to AVSS or AVDD, in order not to have a noise impact to the adjacent analog pins. Tied to AVSS or AVDD More than 1.0uF 2303-E-00 5 2001/09 ASAHI KASEI [AK2303LV] PIN FUNCTION Pin# Name 1 TEST 2 VFTN1 I/O I I Function TEST MODE setting (Please tie to AVSS) 0: Normal mode 1: Test mode Negative analog input of the transmit OPamp(AMPT1) for channel 1. Transmit gain is defined by the ratio of R2/R1. R1 is the external input resister connected to this pin. R2 is the external feedback resister connected between this pin and GST1. Output of the transmit OPamp(AMPT1) for channel 1. Output of the receive OPamp(AMPR1) for channel 1. Negative analog input of the receive OPamp(AMTR1) for channel 1. Receive gain is defined by the ratio of R4/R3. R3 is the external input resister connected to this pin. R4 is the external feedback resister connected between this pin and VR1. Analog Output equivalent to the received PCM data for channel 1. A-law/u-law Select 0A-law 1u-law Positive supply voltage for analog circuit. +3.3V supply. Positive supply voltage for digital circuit. +3.3V supply. Frame sync input. FS must be 8kHz clock which is synchronized with BCLK. Bit clock of PCM data interface. This clock is input for the internal PLL which gerenates the internal system clocks. This clock defines the input/output data rate of DX and DR. The frequency of BCLK should be 2.048MHz or 4.096MHz set via CPU register.. Serial output of PCM data. The channel 1 data is output following the channel 0 data. The PCM data rate is synchronized with BCLK. This output remains in the high impedance state except for the period of transmitting PCM data. Serial input of PCM data. The channel 1 data is received following the channel 0 data. The PCM data rate is synchronized with BCLK. CH1 mute setting 0mute 1normal operation CH0 mute setting 0mute 1normal operation Clock input of serial interface. Data input of serial interface. Read and write enable of serial interface. Pin for PLL loop filter. External capacitance(Min 0.22uF) should be connected between this pin and AVSS. 3 4 5 GST1 GSR1 VFR1 O O I 6 7 8 9 10 11 VR1 ALAWN AVDD DVDD FS BCLK O I I I 12 DX O 13 DR I 14 15 16 17 18 19 MUTE1 MUTE0 SCLK DATA CSN LPC I I I I/O I O 2303-E-00 6 2001/09 ASAHI KASEI Pin# 20 21 22 23 Name VR0 DVSS AVSS VFR0 I/O O I [AK2303LV] Function Analog Output equivalent to the received PCM data for channel 0. Ground for digital circuit. Ground for analog circuit. Negative analog input of the receive OPamp(AMTR0) for channel 0. Receive gain is defined by the ratio of R4/R3. R3 is the external input resister connected to this pin. R4 is the external feedback resister connected between this pin and VR0. Output of the receive OPamp(AMPR0) for channel 0. Output of the transmit OPamp(AMPT0) for channel 0. Positive analog input of the transmit Opamp(AMPT0) for channel 0. MODE select 0Register off mode 1normal mode Analog ground output. External capacitance(1.0 uF) should be connected between this pin and AVSS. 24 25 26 27 28 GSR0 GST0 VFTN0 MODE VREF O O I I O 2303-E-00 7 2001/09 ASAHI KASEI [AK2303LV] CIRCUIT DESCRIPTION Block AMPT0,1 AMPR0,1 Function Op-amp for input gain adjustment. The gain is adjusted with external resistors. The resistor larger than 10k is recommended for the feedback resistor. Op-amp for output gain adjustment. This op-amp is used as an inverting amplifier. The gain is adjusted with external resistors. The resistor larger than 10k is recommended for the feedback resistor. Integrated anti-aliasing filter which prevents signals around the sampling rate from folding back into the voice band. AAF is a 2nd order RC low-pass filter. Converts analog signal to 8bit PCM data according to the companding schemes of ITU recommendation G.711; A-law or u-law. The band limiting filter is also integrated. The selection of companding schemes is set by ALAWN register or hard pin as follows: "H": u-Law "L": A-Law Expands 8bit PCM data according to A-law or u-law. The selection of companding schemes is set by ALAWN register or hard pin as follows: "H": u-Law "L": A-Law Extracts the inband signal from D/A output. It also corrects the sinx/x effect of D/A output. Provides the stable analog ground voltage using an on-chip band-gap reference circuit which is temperature compensated. The output voltage is 1.5V for +3.3V operation. Gain selects of analog I/O signals. It is posibble to select gain from +6dB to -18dB (1dB/step). Gain is defined by the internal register. Interface to the internal register by using SCLK, DATA, and CSN pins. PLL generates system clock of AK2303LV. Reference clock is BCLK More than BCLK LK. 0.22uF capacitance should be connected between LPC and VSS as a PLL Loop filter. PCM data rate is available for 4.096, 2.048MHz which synchronizes with BCLK. Three kinds of data format (Long Frame, Short Frame,GCI) are available. Data format is selected by the register "PCM IF". PCM IF = "L" LongFrame or ShortFrame (LF/SF are selected automatically) PCM IF = "H" GCI PCM data stream, which includes B1 and B2 data, is output through DX pin and input through DR pin. B2 PCM data stream always follows B1 PCM data stream. B1/B2 and Ch0/Ch1 assignment is changed by the SEL2B AAF0,1 A/D D/A SMF BGREF GA0T/R GA1T/R GATN SERIAL I/F PLL PCM I/F 2303-E-00 8 2001/09 ASAHI KASEI [AK2303LV] FUNCTIONAL DESCRIPTION PCM Data Interface AK2303LV supports the following 3 PCM data formats Long Frame Sync(LF) Short Frame Sync(SF) GCI PCM data of both channels are multiplexed and interfaced through the common pins(DR,DX).The first 8bit is defined as B1 channel and the seconds 8bit is defined as B2 channel in the PCM data stream. The order of PCM data is MSB first in each channel. Selection of the interface mode The GCI and ordinary PCM interface(LF,SF) are selectable through the CPU register as following table. Either LF or SF is automatically selected by means of detecting the length of 8KHz frame signal in AK2303LV when PCM I/F is set to "0". Register for PCM Interface mode select(Address:100 PCMIF PCM Interface 0 1 LF or SF GCI Bit:5) Comments LF/SF are selected automatically Default value after power-on reset =LF/SF mode(PCMIF=0). LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic LF/SF selection AK2303LV monitors the duration of the FS "H" level and selects either LF or SF interface format automatically. Period of FS="H" more than 2 clocks of BCLK 1 clock of BCLK Timing of the interface Interface format LF SF 16 bits PCM data (B1 and B2) is accommodated in 1 frame (125us) defined by 8kHz frame sync signal. Although there are 32 time slots at maximum in 8kHz frame (when BCLK=4.096MHz), PCM data for AK2303LV occupy one time slot for channel 0 and channel 1, as is indicated in following. Frame Sync signal (FS) 8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. Bit Clock (BCLK) BCLK defines the PCM data rate. BCLK can be varied 4.096, 2.048MHz. All internal clock of the LSI is generated based on this BCLK signal. Register for BCLK frequency select(Address:101 Bit:7,6) CLKSEL[1:0] BCLK frequency 00 01 10 11 Reserved Reserved 2.048MHz 4.096MHz comments Default value 2303-E-00 9 2001/09 ASAHI KASEI Position of the Ch0,Ch1 PCM data in the DX/DR data flow [AK2303LV] B1 and B2 channel of the PCM data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B register. Time-slot on PCM High-way (Time-slot#0~31(MAX)) can be also assigned for B1 and B2 channel data set as is defined by TS[4:0] register. Channel selection CH0,1selection(Address:100 SEL2B CH0 0 1 B1 B2 Analog Interface Channe0 B1 Channel 1 B2 Bit:6) CH1 B2 B1 PCM Interface Remarks Default on Reset SEL2B Time slot Assignment B1, B2 Time-slot selection (Address:101 Bit:4~0) TS[4:0] Time slot B1 B2 The first half of 8bit The latter half of 00000 0 in Time-slot#0 8bit in Time-slot#0 00001 to The first half of 8bit The latter half of XX 11110 in Time-slot#XX 8bit in Time-slot#XX The first half of 8bit The latter half of 11111 31 in Time-slot#31 8bit in Time-slot#31 FS Time slot# ex) Remarks Default On Reset TS#0 B1 B2 TS#1 DR/X TS#2 TS#3 TS#31(max) B1 Default ex) DR/X B1 B2 TS[4:0]=2 setting 2303-E-00 10 2001/09 ASAHI KASEI Long Frame [AK2303LV] FS BCLK B1 ch B2 ch DX DR Don't care 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 Don't care SEL2B=0 SEL2B=1 B1-CHANNEL (CH0) B1-CHANNEL (CH1) B2-CHANNEL (CH1) B2-CHANNEL (CH0) Short Frame FS BCLK B1 ch B2 ch DX DR Don't care 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 Don't care SEL2B=0 SEL2B=1 B1-CHANNEL (CH0) B1-CHANNEL (CH1) B2-CHANNEL (CH1) B2-CHANNEL (CH0) ! Important Notice Please set time-slot selection as proper value. Maximum time slot is determined from clock speed. At the power up sequence, please set the mute by MUTE0/1 before power up. Then release them after the CODEC initialization and TS assignment to avoid the PCM output data collision with other CODEC's PCM output. Please don't stop feeding FS and BCLK except in Full power down mode. Internal PLL does free running when BCLK is not provided. 2303-E-00 11 2001/09 ASAHI KASEI GCI ( General Circuit Interface ) GCI data format and clocking which is used for ISDN application is shown as following. 4.096, 2.048MHz can be used for BCLK. Thus, data rate will be 2.048 or 1.024MHz. [AK2303LV] Timing of the interface 8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal. Although there are 16 time slots at maximum in 8kHz frame(when BCK=4.096MHz), PCM data on GCI occupy one time slot for channel 0 and channel 1, as is indicated in following. Frame Sync signal (FS) 8kHz reference signal. This signal indicates the timing and the frame position of 8kHz GCI. High level duration of the FS is 1 clock period of BCLK. Bit Clock (BCLK) BCLK defines the GCI data rate. All the internal clock of the LSI is generated based on this BCLK signal. The data rate of GCI is half of BCLK. BCLK can be used either 4.096MHz or 2.048MHz. Position of the Ch0,Ch1 GCI data in the DX/DR data flow B1 and B2 channel of the GCI data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B register as same way as PCM interface. Time-slot also can be assigned by same way as PCM format. Channel selection CH0,1selection(Address:100 SEL2B CH0 0 1 B1 B2 Bit:6) CH1 B2 B1 Remarks Default On Reset Analog Interface Channe0 PCM Interface B1 Channel 1 B2 SEL2B Time slot Assignment B1, B2 Time-slot selection (Address:101 Bit:4~0) TS[4:0] Time slot B1 B2 The first half of 8bit The latter half of 00000 0 in Time-slot#0 8bit in Time-slot#0 00001 to The first half of 8bit The latter half of XX 01110 in Time-slot#XX 8bit in Time-slot#XX The first half of 8bit The latter half of 01111 15 in Time-slot#15 8bit in Time-slot#15 Remarks Default On Reset 2303-E-00 12 2001/09 ASAHI KASEI FS Time slot# ex) [AK2303LV] TS#0 TS#1 DR/X TS#2 TS#3 TS#15(max) B1 Default ex) B1 B2 DR/X B1 B2 TS[4:0]=2 setting GCI FS BCLK B1 ch B2 ch DX DR Don't care 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 Don't care SEL2B=0 SEL2B=1 B1-CHANNEL (CH0) B1-CHANNEL (CH1) B2-CHANNEL (CH1) B2-CHANNEL (CH0) ! Important Notice Please set time-slot selection as proper value. Maximum time slot is determined from clock speed. At the power up sequence, please set the mute by MUTE0/1 before power up. Then release them after the CODEC initialization and TS assignment to avoid the PCM output data collision with other CODEC's PCM output. Please don't stop feeding FS and BCLK except in Full power down mode. Internal PLL does free running when BCLK is not provided. 2303-E-00 13 2001/09 ASAHI KASEI [AK2303LV] MUTE The output on each channel can be muted independently through the CPU register as shown in the table. Mute register( Address:100 Bit:5,4 ) MTCH0,1 0 1 Operation Normal Mute DX pin PCM data output High-Impedance( *1) VRX pin CODEC analog output AGND* (*1) MTCH0 and MTCH1 are the mute control bit for CH0 and CH1,respectively. B1 and B2 channel muted by MTCH0/1 is defined by SEL2B bit shown in the PCM Interface section. FS0 BCLK DX DR Don't care B1-CHANNEL(CH0) 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 Don't care B2-CHANNEL(CH1) VRX0 VRX1 GCI mode : : CODEC CH0 analog output is always at AGND level. CODEC CH1 analog output is the signal converted from the PCM data of CH1 input through DR pin. CH0 mute (MTCH0=1, MTCH1=0, SEL2B=0) FS0 BCLK DX DR Don't care B1-CHANNEL(CH0) 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 Don't care B2-CHANNEL(CH1) VRX0 VRX1 : : CODEC CH0 analog output is always at AGND level. CODEC CH1 analog output is the signal converted from the PCM data of CH1 input through DR pin. 2303-E-00 14 2001/09 ASAHI KASEI [AK2303LV] GAIN ADJUSTMENT Analog input/output gain can be adjusted at the range from +6dB to -18dB by 1.0dB step through CPU register. VR Register( Address:011 -000 Bit:4 -0) GanT4 GanR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 GanT3 GanR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 GAnT2 GAnR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 --- GAnT1 GAnR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 --- GAnT0 GAnR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 --- Gain [dB] +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 Remarks Default 2303-E-00 15 2001/09 ASAHI KASEI [AK2303LV] RESET Power on Reset AK2303LV automatically generates the internal reset pulse which resets all the circuit that is necessary to start the initialization after the power on reset. The CPU registers are set to the default value. After the internal reset pulse is generated, CODEC Ch0/Ch1 starts the initialization procedure by being fed FS signal, and it takes 180ms( typ.), 350ms(max) to complete the initialization after the detection of power on. Power up slope to enable the Power-on Reset When power-up slope is no longer than 50ms(=5tau:tau is time constant), Power On Reset works normally. When the time is longer than 50ms, Power On Reset is not activated and no internal registers are initialized. In this case all registers must be written through CPU interface. NOTE) For stable operation after power up, we recommend to write all register value through CPU interface after power up. Recommended start up procedure The following start up procedure is recommended when AK2303LV is going to power up. Power up Wait 200ms *In case of VDD rising time =50ms(=5tau) - FS="L" - BCLK="L" - MUTE 0/1="L" When 1stFS and BCLK are set to "L", CODEC ch0,ch1 dose not interface with external devices. Write data to the internal register through serial I/F - Write data to the internal register before CODEC starts working. Supply FS and BCLK - CODEC Initialization starts. Wait 130ms - CODEC Initialization complete. - MUTE 0/1="H" CODEC starts working 2303-E-00 16 2001/09 ASAHI KASEI [AK2303LV] POWER DOWN Power consumption is reduced in the power down mode. In the power down mode, the current fed to analog circuits and the clock for digital circuits, are stopped, and the related circuits hold its current status. There are two power down modes. - Power down for all circuits - Power down by block * In the power down mode, the output pins of corresponding blocks turn to Hi-Z. (See page 5) POWER DOWN MODE SETTING 2 power down modes Mode Circuits Registers Operation for "0"/"1" Note - CPU Registers are not reset.(hold its value) - Serial I/F is available. - No need to supply FS, BCLK. - Keep supplying FS and BCLK. - AMPTn, AMPRn(n=0,1) Input/Output is active, even when CODEC CHn(n=0,1) is in power down mode, Please refer table of the next page in detail. All circuit All PD "0" : Normal "1" : Power down CODEC CH0 Block CODEC CH1 PDCH0 "0" : Normal "1" : Power down PDCH1 WAKE UP FROM POWER DOWN MODE After power down mode for CODEC CH0/CH1 is cleared, the CODEC circuit starts to be initialized. It takes 130mS(typ). WAKE UP FROM FULL POWER DOWN MODE When full circuit power down mode for CODEC is cleared, AK2303LV starts the same wake up sequence as one at power on. It takes 250ms(typ). 2303-E-00 17 2001/09 ASAHI KASEI POWER DOWN BLOCK REGISTER AMPT0 GA0T Channel 0 AAF0 CODEC CH0 SMF0 GA0R AMPR0 AMPT1 GA1T Channel 1 AAF1 CODEC CH1 SMF1 GA1R AMPR1 PCM I/F PLL BGREF SERIAL I/F ALL BLOCK PD OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF CODEC CH0 PDCH0 CODEC CH1 PDCH1 CODEC CH0&1 PDCH0 PDCH1 [AK2303LV] 2303-E-00 18 2001/09 ASAHI KASEI [AK2303LV] SERIAL INTERFACE The internal registers can be read/written with SCLK, DATA, and CSN pins. 1word consists of 16bits. The first 4bits are the instruction code which specifies read/write. The following 3bits specify the address. The rest of 8bits are for setting registers. B15 I3 B14 I2 B13 I1 B12 I0 B11 A2 B10 A1 Address (3bit) B9 A0 B8 * * B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0 Instruction code (4bit) Data for internal registers (8bit) *)Dummy bit for adjusting the I/O timing when reading register. INSTRUCTION CODEC I3 1 1 I2 1 1 I1 1 1 I0 0 1 Read/Write Read Write No action Other codes SCLK and WRITE/READ (1) Input data are loaded into the internal shift register at the rising edge of SCLK. (2) The rising edge of SCLK is counted after the falling edge of CSN. (3) When CSN is "L" and more than 16 SCLK pulses: th [WRITE] Data are loaded into the internal register at the rising edge of the SCLK 16 pulse. th [READ] DATA pin is switched to an input pin at the falling edge of the SCLK 16 pulse. CSN and WRITE / READ CANCELLATION (1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16 pulse. th (2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16 pulse. SERIAL WRITE / READ (SERIAL ACCESS) th (1) CSN must go up to "H" before the next access in successive access. (2) When the next access is going to be done , if CSN remains to be "L", successive access can not be done. 2303-E-00 19 2001/09 ASAHI KASEI WRITE Continuous SCLK Must goes up once Goes up anytime after SCLK 16th pulse [AK2303LV] CSN SCLK DATA Z 1 2 3 4 5 6 7 8 9 16 1 2 3 4 8 9 15 16 1 1 1 1 0 0 0 * D7 D0 Z 1 1 1 1 D7 D1 D0 Z Instruction Code Address "000" Write data to address"000" WRITE at the rising edge of SCLK 16th pulse Instruction Code Write data Burst SCLK SCLK can be stop at "H" level or "L" level at anytime during the write cycle. After resuming the SCLK, write cycle is retrieved normally. Must go up once Goes up anytime after SCLK 16th pulse CSN SCLK DATA Z 1 2 3 4 5 6 7 8 9 16 1 1 1 1 0 0 0 * D7 D0 Z Instruction Code Address "000" Write data to address "000" WRITE at the rising edge of SCLK 16th pulse CANCELLATION CSN goes "H" before the rising edge of 16th SCLK pulse CS SCLK DATA Z 1 2 3 4 5 6 7 8 9 16 1 1 1 1 0 0 0 * D7 D0 Z Instruction Code Address "000" Write data to address"000" Write is not Excuted Z DATA pin : Input mode (Hi-Z) 2303-E-00 20 2001/09 ASAHI KASEI SERIAL ACCESS Serial access with CSN staying "L" during the serise of write cycle. CS SCLK DATA Z 1 2 3 4 5 6 7 8 9 16 1 2 3 4 8 9 [AK2303LV] 15 16 1 1 1 1 0 0 0 * D7 D0 Z 1 1 1 1 D7 D1 Write data D0 Z Instruction Code Address "000" Write data to Address"000" EXCUTE! Instruction Code NOT EXCUTED! READ CONTINOUS SCLK Must go up once Can be going up at anytime after SCLK 16th pulse CS SCLK DATA Z 1 2 3 4 5 6 7 8 9 16 1 2 3 4 8 9 15 16 1 1 1 0 A2 A1 A0 Z D7 D0 Z 1 1 1 0 D7 D1 D0 Z Read Instruction Address Read Data Read Instruction Read Data Data output starts at the falling edge of SCLK 8th pulse Read period until the earlier edge of either CSN rising or SCLK 16th pulse falling Burst SCLK Must go up once Can be going up at anytime after SCLK 16th pulse CS SCLK DATA Z 1 2 3 4 5 6 7 8 9 16 1 1 1 0 A2 A1 A0 Z D7 Read Data D0 Z Read Instruction Address Read output starts at the falling edge of SCLK 8th pulse 2303-E-00 21 2001/09 ASAHI KASEI SERIAL ACCESS Serial access with CSN staying "L" during the serise of read cycle. [AK2303LV] CS SCLK DATA Z 1 2 3 4 5 6 7 8 9 16 1 2 3 4 8 9 15 16 1 1 1 0 0 0 0 Z D7 D0 Z 1 1 1 0 Z Read Instruction Address "000" Read data READ EXCUTED! Read Instruction READ NOT EXCUTED! DISCORD OF INSTRUCTION CODE CS SCLK DATA Z 1 2 3 4 5 6 7 8 9 16 I3 I2 I1 I0 A2 A1 A0 Address Z IInstructions except specified 0bbb 10bb 110b (b=0 or 1) WRITE/READ NOT EXCUTED! Z DATA pin: Input mode (Hi-Z) 2303-E-00 22 2001/09 ASAHI KASEI [AK2303LV] MODE SETTING AK2303LV has a normal mode and a register off mode set by MODE pin. (pin#27) In nomal mode, all registers are able to be accessed through the serial interface and the various functions listed in the table of the next page can be controled via the interface. In register off mode, all registers except volume are forced to defult value. The register off mode eliminates the fatal abnormal condition of system caused by the crush of the internal register value whitch may occurr due to the lightning, the strong electromagnetic field and quick power supply change. MODE Normal mode: 1.All registers can be accessed. 2. It iis highly recommended that all the register are to be written periodically and after the abnormal circumstances happens. MODE="L" (AVSS) Register off mode: 1.Register data of address "100" and "101" are forced to defult value. The register of adress "000" to "001" are remain to be accessed. 2.ALAWN, MUTE1 and MUTE0 setting are valid only from pin setting. Attention: Please connect MODE pin to AVSS or AVDD. MODE pin status MODE="H" (AVDD) 2303-E-00 23 2001/09 ASAHI KASEI [AK2303LV] REGISTER Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 MAP Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 * * * * * * * * * D7 0 0 0 0 ALAWN CLKSEL1 D6 0 0 0 0 SEL2B CLKSEL0 D5 PCMIF - D4 GA0R4 GA1R4 GA0T4 GA1T4 MTCH1 TS4 D3 GA0R3 GA1R3 GA0T3 GA1T3 MTCH0 TS3 D2 GA0R2 GA1R2 GA0T2 GA1T2 PD TS2 D1 GA0R1 GA1R1 GA0T1 GA1T1 PDCH1 TS1 D0 GA0R0 GA1R0 GA0T0 GA1T0 PDCH0 TS0 Reserved Reserved *) Dummy Bit Note) All registers except "0" and "Reserved" can read/write. Note) "0" bit data can not be written, however "0" data will be output when it is read. Note) When mode pin is "L", register address "100" and "101" is fixed to default value. INITIALIZATION OF REGISTERS The registers are initialized at POWER ON RESET only. Power on reset may not be excuted due to the difference of power up time constant. Thus it is highly recommended that all the register (address(000 - 101) ) are to be written at the time of the power up and after the abnormal circumstances happens such as micro interrupt of the power line or mal operation due to lightning. REGISTER FUNCTION Address 000 001 Bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Name GA0R0 GA0R1 GA0R2 GA0R3 GA0R4 GA1R0 GA1R1 GA1R2 GA1R3 GA1R4 - Default 0 1 1 0 0 Function Receive gain adjustment on ch0 +6 to -18dB by 1.0dB step 00000: +6dB 11xxx: -18dB Refer 0 1 1 0 0 Receive gain adjustment on ch1 +6 to -18dB by 1.0dB step 00000: +6dB 11xxx: -18dB 2303-E-00 24 2001/09 ASAHI KASEI Address 010 Bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 101 0 1 2 3 4 5 6 7 110 Name GA0T0 GA0T1 GA0T2 GA0T3 GA0T4 GA1T0 GA1T1 GA1T2 GA1T3 GA1T4 PDCH0 PDCH1 PD MTDX0 MTDX1 PCMIF SEL2B ALAWN TS0 TS1 TS2 TS4 TS5 CLKSEL0 CLKSEL1 Default 0 1 1 0 0 Function Transmit gain adjustment on ch0 +6 to -18dB by 1.0dB step 00000: +6dB 11xxx: -18dB Refer [AK2303LV] 011 0 1 1 0 0 Transmit gain adjustment on ch1 +6 to -18dB by 1.0dB step 00000: +6dB 11xxx: -18dB 100 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 CODEC CH0,1 Power down control 0: Power ON 1: Power OFF Full Power down 0: Power ON 1: Power OFF Mute control: VR0.VR1,DX pin 0: Normal output 1: Mute PCM Interface select 0: LF/SF 1: GCI PCM data channel select 0: CH0B1 1: CH1B1 A/u-law select 0: A-law 1: -law Time slot setting 4.096MHz : 0 to 31 2.048MHz : 0 to 15 1.024MHz : 0 to 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 * Please set the same frequency as BCLK input. BCLK frequency setting * CLKSEL[1:0]= 00: (Reserved) 01: (Reserved) 10: 2.048MHz 11: 4.096MHz Reserved 2303-E-00 25 2001/09 ASAHI KASEI Address 111 Bit 0 1 2 3 4 5 6 7 Name Default 0 0 0 0 0 0 0 0 Function Reserved Refer [AK2303LV] 2303-E-00 26 2001/09 ASAHI KASEI MUTE 0 MUTE 1 Mute setting register MTCH 0 R [AK2303LV] Internal MUTE0 signal ( 1:Mute ) ( default: 0 ) Internal MUTE1signal MTCH 1 R ( default: 0 ) ( 1:Mute ) ALAWN Internal A-law signal S ALAWN ( default: 1 ) ( 0: A-law, 1:u-law ) A-law /u-law setting register MODE Power-On Reset Circuit Internal Reset signal (Active high signal ) 2303-E-00 27 2001/09 ASAHI KASEI [AK2303LV] ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltages Analog/Digital Power Supply VSS Voltage Symbol Min Max AVDD DVDD -0.3 6.5 AVSS -0.1 0.1 DVSS Digital Input Voltage VTD -0.3 VDD+0.3 Analog Input Voltage VTA -0.3 VDD+0.3 Input current (except power supply pins) IIN -10 10 Storage Temperature Tstg -55 125 Warning: Exceeding absolute maximum ratings may cause permanent damage. Normal operation is not guaranteed at these extremes. Units V V V V mA o C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supplies VDD Analog/Digital power supply Ambient Operating Temperature Ta Frame Sync Frequency FS Note) All voltages reference to ground : VSS=0V Min 3.0 -40 8 Typ 3.3 Max 3.6 85 Units V C kHz o ELECTRICAL CHARACTERISTICS Unless otherwise noted, guaranteed for VDD=+3V0.3V, Ta = -40 ~ +85 C, FS=8kHz. o DC Characteristics Parameter Power Consumption BCLK=2048kHz Output High Voltage (CMOS level) Output Low Voltage (CMOS level) Input High Voltage1 (CMOS level) Input Low Voltage1 (CMOS level) Input Leakage Current Input Capacitance Output Leakage Current Symbol PDD1 PDDd VOH VOL VIH1 VIL1 Ii Ci Io -10 Tri-state mode -10 Conditions PDCH0,1 =0,0 All output unloaded PD = 1 Power down IOH=-1.6mA IOL=1.6mA 0.7VDD 0.3VDD +10 5 +10 Min Typ 35 mW 2.5 0.8VDD 0.4 V V V V uA pF uA Max Units 2303-E-00 28 2001/09 ASAHI KASEI CODEC Absolute Gain (VDD=3.3V 0.3V ) Parameter Conditions Analog Input Level Input: 0dBm0@1020Hz Absolute Transmit Gain (Typ) Analog Output Level Absolute Receive Gain Maximum Overload Level Input: 0dBm0@1020Hz (Typ) +3.14dBm0 [AK2303LV] Min (-0.15) -0.25 (-0.15) -0.25 Typ 0.531 0.531 0.762 Units Vrms (+0.15) dB +0.25 dB Vrms (+0.15) dB +0.25 dB Vrms Max * Power supply and the temperature are in typical condition. Gain Tracking Parameter Transmit Gain Tracking Error Receive Gain Tracking Error Conditions Reference Level: -55dBm0 ~-50dBm0 -10dBm0 -50dBm0 ~-40dBm0 1020Hz Tone -40dBm0 ~ 3dBm0 Reference Level: -55dBm0 ~-50dBm0 -10dBm0 -50dBm0 ~-40dBm0 1020Hz Tone -40dBm0 ~ 3dBm0 Min -1.2 -0.4 -0.2 -1.2 -0.4 -0.2 Typ - Max 1.2 0.4 0.2 1.2 0.4 0.2 Units dB dB Frequency Response Parameter Transmit Frequency Response Receive Frequency Response Conditions Relative to: 0.05kHz 0dBm0@1020Hz 0.06kHz 0.2kHz 0.3 ~3.0kHz 3.4kHz 4.0kHz Relative to: 0 ~3.0kHz 0dBm0@1020Hz 3.4kHz 4.0kHz Min -1.8 -0.15 -0.8 -0.15 -0.8 - Typ - Max -30 -26 0 0.15 0 -14 0.15 0 -14 Units dB dB Distortion Parameter Transmit Signal to Distortion Conditions -40dBm0 ~-45dBm0 -30dBm0 ~-40dBm0 0dBm0 ~-30dBm0 1020Hz Tone -40dBm0 ~-45dBm0 -30dBm0 ~-40dBm0 0dBm0 ~-30dBm0 1020Hz Tone Min 25 30 36 25 30 36 Typ Max -46 -46 -42 Units dB Receive Signal to Distortion dB dB dB dB Single Frequency Distortion Transmit Single Frequency Distortion Receive Intermodulation Distortion -6dBm@860Hz,1380Hz Note) C-message Weighted for u-Law, Psophometric Weighted for A-Law 2303-E-00 29 2001/09 ASAHI KASEI Envelope delay Distortion Parameter Transmit Delay, Absolute Transmit Delay, Relative Conditions f =1600Hz f =500Hz ~600Hz f =600Hz ~1000Hz f =1000Hz ~2600Hz f =2600Hz ~2800Hz f =2800Hz ~3000Hz f =1600Hz f =500Hz ~1000Hz f =1000Hz ~1600Hz f =1600Hz ~2600Hz f =2600Hz ~2800Hz f =2800Hz ~3000Hz Min -40 -30 Typ - [AK2303LV] Max 360 220 145 75 105 155 240 90 125 175 Units us us Relative to f=1600Hz Receive Delay, Absolute Receive Delay, Relative us us Relative to f=1600Hz Noise Conditions Min u-law, C-message A-law, Psophometric u-law, C-message A-law, Psophometric VFXIN = 0 Vrms, DR = DX f=0 ~100kHz PSRR, Transmit AVDD=DVDD=5V100mVop 40 f=0 ~50kHz PSRR, Receive AVDD=DVDD=5V100mVop 40 f=0 ~50kHz Spurious Out-of-Band Signal 0dBm0, 4.6 ~7.6kHz 3) at VRX Output 0.3 ~3.4kHz 7.6 ~8.4kHz PCM CODE 8.4 ~100kHz Note 1) Analog Input = Analog Ground Note 2) Digital Input(DR) = +0 Code Note 3) Not tested in production Test. Parameters guaranteed by design. Interchannel Crosstalk Parameter Transmit to Receive Receive to Transmit Transmit to Transmit Receive to Receive Intrachannel Crosstalk Parameter Transmit to Receive Receive to Transmit Parameter Load Resistance Load Capacitance Output voltage Swing Parameter 1) Idle Channel Noise AD 2) Idle Channel Noise DA Noise, Single Frequency Typ 0 90 0 90 Max 10 -80 10 -80 -53 -30 -40 -32 Units dBrnC0 dBm0p dBrnC0 dBm0p dBm0 dB dB dB Conditions 0dBm0@VFXIN, Idle PCM code 0dBm0 code level, VFXIN = 0 Vrms 0dBm0@VFXIN, Idle PCM code 0dBm0 code level, VFXIN = 0 Vrms Min - Typ - Max -75 -75 -75 -75 Units dB dB dB dB Conditions 0dBm0@VFXIN, Idle PCM code 0dBm0 code level, VFXIN = 0 Vrms Conditions Min Min 10 - Typ Typ 2.25 Max -75 -75 Max 50 Units dB dB Units k pF Vp-p Analog Interface Transmit Amplifier GSTn(n=0,1) 2303-E-00 30 2001/09 ASAHI KASEI Analog Interface Receive Output (VDD: 3.3V0.3V) Parameter Conditions Output voltage(AGND level) +0 PCM code input Load Resistance Load Capacitance Output voltage Swing VRn(n=0,1) Analog Interface Receive Output Amplifier [AK2303LV] Min 10 Typ 1.5 Max 50 Units V k pF Vp-p 2.25 Parameter Load Resistance Load Capacitance Output Voltage Swing Conditions GSRn(n=0,1) Min 10 - Typ 2.25 Max 50 - Units k pF Vp-p VOLUME ( GA0T,GA0R,GA1T,GA1R) Parameter Step margin Pin Conditions Relative to: 0dB Min -1.0 typ max Unit +1.0*) dB *)Monotonus increase/decrease is guranteed 2303-E-00 31 2001/09 ASAHI KASEI PCM INTERFACE ( Long Frame, Short Frame, GCI ) [AK2303LV] o Unless otherwise noted, the specification applies for TA = -40 to +85 C, VDD = 5V5%/3V0.3V,VSS = 0V and FS0= 8kHz. All timing parameters are measured at VOH = 0.8VDD and VOL =0.4V. Parameter FS Frequency BCLK Frequency BCLK Pulse Width High BCLK Pulse Width Low Rising Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Falling Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Hold Time: BCLK Low to FS High Setup Time: FS High to BCLK Low Setup Time: DR to BCLK Low Hold Time: BCLK Low to DR Delay Time: BCLK High to DX valid Long Frame Hold Time: 2 period of BCLK Low to FS Low Delay Time: FS or BCLK High, whichever is later,to DX valid Note1) Delay Time: BCLK Low to DX High-Z FS Pulse Width Low Short Frame Hold Time: BCLK Low to FS Low Setup Time: FS Low to BCLK Low Delay Time: BCLK Low to DX High-Z GCI BCLK Frequency Delay Time: Second BCLK Low to DX High-Z Setup Time: DR to Second BCLK High Hold Time: Second BCLK High to DR 1/tPBG tDZCG tSDBG tHBDG 2048 10 40 40 4096 60 kHz ns Fig3 ns ns Note1) tHBFS tSFBS tDZCS 40 40 10 60 ns ns ns Fig2 Note1) nd Symbol 1/tPF 1/tPB tWBH tWBL tR tF tHBF tSFB tSDB tHBD Note1) tDBD Min 2048 80 80 Typ 8 Max 4096 Units Ref Fig kHz kHz ns ns 40 40 40 70 40 40 60 ns ns ns ns ns ns ns Fig1 Fig2 Fig3 tHBFL tDZFL tDZCL tWFSL 40 60 10 1 60 ns ns Fig1 ns BCL K Note1) Measured with 150pF Load capacitance and driving two LSTTLs 2303-E-00 32 2001/09 ASAHI KASEI tFB BCLK tSF tHBFL tRB tWBL tWBH tPB [AK2303LV] FS tHBF DX MSB 2 3 tSD DR MSB 2 3 4 tHB 4 5 6 7 8 5 6 7 8 tDZF tDB tDZC FS tPF tWFSL Fig1 PCM Interface Timing < Long Frame > tFB BCLK tRB tWB tWBH tPB tSF tHBF FS tHBF DX MSB 2 3 tSD DR MSB 2 3 4 4 tHB 5 6 7 8 5 6 7 8 tSFB tDBD tDBD tDZC Fig2 PCM Interface Timing < Short Frame > 2303-E-00 33 2001/09 ASAHI KASEI [AK2303LV] FS 1 2 3 4 5 6 7 8 9 10111213141516 BCLK tDB DX MS 2 3 tSDB DR MS 2 3 4 4 5 tHBD 5 6 7 8 MS 2 3 4 5 6 7 8 6 7 8 tDZC MS 2 3 4 tWB 5 6 7 8 tPB tWB BCLK tSF FS tHBF DX 1 2 3 tDZFL tHBFS tWFSL Fig3 PCM Interface Timing < GCI > 2303-E-00 34 2001/09 ASAHI KASEI SERIAL INTERFACE Parameter SCLK Frequency SCLK Pulse Width High SCLK Pulse Width Low CS(bar) Pulse Width Low Hold Time: SCLK High to CS(bar) Low Setup Time: CS Low to SCLK High Rising Time: CS(bar),SCLK Falling Time: CS(bar),SCLK Symbol 1/tPSCLK tWSH tWSL tWCL tHCS tSCS tR tF 40 40 16 80 40 100 100 Min Typ Max 4 [AK2303LV] Units Ref fig MHz ns ns SCL K ns ns ns ns Fig4 WRITE Setup Time: DATA to SCLK High Hold Time: SCLK High to DATA Hold Time: SCLK Low to CS(bar) High tSDC tHDC tHCS2 40 40 0 ns ns ns Fig4 READ Delay Time: SCLK Low to DATA pin drive Delay Time: SCLK Low to DATA valid Delay Time: SCLK Low to DATA High-Z Delay Time: CS High to DATA High-Z CS(bar) Pulse Width High tDDD tDVD tDZSD tDZCD tWCH 0 0 40 0 60 60 60 ns Fig5 ns ns ns ns Fig6 2303-E-00 35 2001/09 ASAHI KASEI tWCL CS(bar) tHC SCLK tHDC tSC DATA I3 tSD I2 I0 A2 A0 * D D6 D tWSH tWSL tPSC tF tR [AK2303LV] tHC Fig4 Serial Interface Timing tWCL CS(bar) tHCS tWSH tWSL tPSCLK tF tR tHCS SCLK tHDC tSC tSD tDDD Z I2 I0 A2 A0 D7 D6 D1 D0 tDVD DATA I3 Fig5 Serial Interface Timing tWCH CS(bar) SCLK tDZSD tDZCD Z Z DATA D1 D0 I1 I0 D0 Fig6 Serial Interface Timing 2303-E-00 36 2001/09 ASAHI KASEI [AK2303LV] APPLICATION CIRCUIT EXAMPLE Analog input circuit(AMPT0,1) AK2303LV has an op-amp at analog input of each channel. Each op-amp can be used as a gain adjustment. Op-amp can be used as an inverting amplifier. Feedback resistor must be 10k or larger. AK2303LV GSTn R2 (n=0,1) C1 R1 VFTn C1=0.47uF R1=R2=33K ohm AMPTn Analog output circuit(AMPR0,1) AK2303LV has an op-amp at analog output stage of each channel to consist in an inverting amplifier for a gain adjustment of 0dBm0 level. Feedback resistor must be 10k or larger. AK2303LV GSRn BGREF (n=0,1) R1 R1=R2=33K ohm R2 VRn GAnR VFRn 2303-E-00 37 2001/09 ASAHI KASEI [AK2303LV] Analog ground stabilization capacitor An external capacitor of more than 1.0uF should be connected between VREF and VSS to stabilize analog ground (VREF). AK2303LV VREF AVSS C + PLL Loop filter capcitor An external capacitor of more than 0.22uF should be connected between LPC and VSS. AK2303LV LPC AVSS C + Power Supply To attenuate the power supply noise, connect capacitors between VDD and VSS, as shown below. A K 230 3LV AVDD + C1 C2 C 1= 0.1 F C 2= 10F AVSS D VD D + C1 C2 D V SS 2303-E-00 38 2001/09 ASAHI KASEI [AK2303LV] PACKAGE INFORMATION - 28pin VSOP Marking (1) Date Code and Lot#: 9 digit XXXXXXXXX (2) Marketing Code: AK2303LV (3) AKM Logo AK2303LV AKM AK2303LV XXXXXXXXX 2303-E-00 39 2001/09 ASAHI KASEI [AK2303LV] 28pin VSOP (Unit: mm) *9.80.2 28 15 A 7.60.2 0.15+0.10 -0.05 0.100.05 Detail A 0.10 0-10 40 1 0.65 0.12 14 0.22+0.10 -0.05 M 5.6 1.15 Seating Plane 0.08 NOTE: Dimension "*" does not include mold flash. 2303-E-00 0.50.2 2001/09 ASAHI KASEI * * * * [AK2303LV] * IMPORTANT NOTICE These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. 2303-E-00 41 2001/09 |
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